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? 2005 fairchild semiconductor corporation ds500864 www.fairchildsemi.com october 2003 revised april 2005 fin3385 ? fin3383 fin3384 fin3386 low voltage 28-bit flat panel display link serializers/deserializers fin3385 fin3383 fin3384 fin3386 low voltage 28-bit flat panel display link serializers/deserializers general description the fin3385 and fin3383 transform 28 bit wide parallel lvttl (low voltage ttl) data into 4 serial lvds (low voltage differential signaling) data streams. a phase- locked transmit clock is transmitted in parallel with the data stream over a separate lvds link. every cycle of transmit clock 28 bits of input lvttl data are sampled and trans- mitted. the fin3386 and fin3384 receive and convert the 4/3 serial lvds data streams back into 28/21 bits of lvttl data. refer to table 1 for a matrix summary of the serializ- ers and deserializers available. for the fin3385, at a transmit clock frequency of 85mhz, 28 bits of lvttl data are transmitted at a rate of 595mbps per lvds channel. these chipsets are an ideal solution to solve emi and cable size problems associated with wide and high-speed ttl interfaces. features low power consumption 20 mhz to 85 mhz shift clock support r 1v common-mode range around 1.2v narrow bus reduces cable size and cost high throughput (up to 2.38 gbps throughput) internal pll with no external component compatible with tia/eia-644 specification devices are offered 56-lead tssop packages ordering code: devices also available in tape and reel. specify by appending suffix letter ?x? to the ordering code. table 1. display panel link serializers/deserializers chip matrix order number package number package description fin3383mtd mtd56 56-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide fin3384mtd mtd56 56-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide fin3385mtd mtd56 56-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide FIN3386MTD mtd56 56-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide part clk frequency lvttl in lvds out lvds in lvttl out package fin3385 85 28 4 56 tssop fin3383 66 28 4 56 tssop fin3386 85 4 28 56 tssop fin3384 66 4 28 56 tssop
www.fairchildsemi.com 2 fin3385 fin3383 fin3384 fin3386 block diagrams functional diagram for fin3385 and fin3383 receiver functional diagram for fin3386 and fin3384
3 www.fairchildsemi.com fin3385 fin3383 fin3384 fin3386 transmitters pin descriptions connection diagram fin3383 and fin3385 (28:4 transmitter) pin assignment for tssop truth table h high logic level l low logic level x don?t care z high impedance f floating note 1: the outputs of the transmitter or receiver will remain in a high impedance state until v cc reaches 2v. note 2: txclkout r will settle at a free running frequency when the part is powered up, pwrdn is high and the txclkin is a steady logic level (l/h/z). pin names i/o type number of pins description of signals txin i 28/21 lvttl level input txclkin i 1 lvttl level clock input the rising edge is for data strobe. txout o 4/3 positive lvds differential data output txout o 4/3 negative lvds differential data output txclkout o 1 positive lvds differential clock output txclkout o 1 negative lvds differential clock output r_fb i 1 rising edge clock (high), falling edge clock (low) pwrdn i 1 lvttl level power-down input assertion (low) puts the outputs in high impedance state. pll v cc i 1 power supply pin for pll pll gnd i 2 ground pins for pll lvds v cc i 1 power supply pin for lvds output lvds gnd i 3 ground pins for lvds output v cc i 3 power supply pins for lvttl input gnd i 5 ground pins for lvttl input nc no connect inputs outputs txin txclkin pwrdn (note 1) txout r txclkout r active active h l/h l/h active l/h/z h l/h x (note 2) factiveh l l/h f f h l x (note 2) xxlz z
www.fairchildsemi.com 4 fin3385 fin3383 fin3384 fin3386 receivers pin descriptions connection diagram fin3386 and fin3384 (4:28 receiver) pin assignment for tssop pin names i/o type number of pins description of signals rxin i 4/3 negative lvds differential data input rxin i 4/3 positive lvds differential data input rxclkin i 1 negative lvds differential clock input rxclkin i 1 positive lvds differential clock input rxout o 28/21 lvttl level data output goes high for pwrdn low rxclkout o 1 lvttl clock output pwrdn i 1 lvttl level input refer to transmitter and receiver power-up and power-down operation truth table pll v cc i 1 power supply pin for pll pll gnd i 2 ground pins for pll lvds v cc i 1 power supply pin for lvds input lvds gnd i 3 ground pins for lvds input v cc i 4 power supply for lvttl output gnd i 5 ground pin for lvttl output nc no connect
5 www.fairchildsemi.com fin3385 fin3383 fin3384 fin3386 transmitter and receiver power-up/power-down operation truth table the outputs of the transmitter remain in the high-impedance state until the power supply reaches 2v. the following table shows the operation of the transmitter during power-up and power-down and operation of the pwrdn pin. h high logic level l low logic level p last valid state x don?t care z high-impedance note 3: if the transmitter is powered up and pwrdn is inactive high and the clock input goes to any state low, high, or z then the inte rnal pll will go to a known low frequency and stay until the clock starts normal operation again. note 4: if the input is terminated and un-driven (z) or shorted or open. (fail safe condition) note 5: for pwrdn or fail safe condition the rxclkout pin will go low for panel link devices and high for channel link devices. note 6: shorted here means ( r inputs are shorted to each other, or r inputs are shorted to each other and ground or v cc , or either r inputs are shorted to ground or v cc ) with no other current/voltage sources (noise) applied. if the v id is still in the valid range (greater than 100mv) and vcm is in the valid range (0v to 2.4v) then the input signal is still recognized and the part will respond normally. transmitter pwrdn normal v cc 2v ! 2v ! 2v ! 2v ! 2v ! 2v txin x x active active txout z z active x txclkin x x active h/l/z txclkout r z z active (note 3) pwrdnl lhhhh receiver pwrdn rxin r x x active active (note 4) (note 4) rxout z l l/h p h p rxclkin r x x active (note 4) active (note 4) rxclkout z (note 5) active (note 5) (note 5) (note 5) pwrdnl lhhhh v cc 2v 2v 2v 2v 2v 2v
www.fairchildsemi.com 6 fin3385 fin3383 fin3384 fin3386 absolute maximum ratings (note 7) recommended operating conditions note 7: absolute maximum ratings are dc values beyond which the device may be damaged or have its useful life impaired. the datasheet specifica- tions should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading vari- ables. fairchild does not recommend operation outside datasheet specifi- cations. note 8: 100mv v cc noise should be tested for frequency at least up to 2 mhz. all the specification below should be met under such a noise. transmitter dc electrical characteristics over supply voltage and operating temperature ranges, unless otherwise specified. (note 9) note 9: all typical values are at t a 25 q c and with v cc 3.3v. note 10: positive current values refer to the current flowing into device and negative values means current flowing out of pins. voltage are referenced to ground unless otherwise specified (except ' v od and v od ). note 11: the power supply current for both transmitter and receiver can be different with the number of active i/o channels. note 12: the 16-grayscale test pattern tests device power consumption for a ? typical ? lcd display pattern. the test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display. power supply voltage (v cc ) -0.3v to +4.6v ttl/cmos input/output voltage 0.5v to 4.6v lvds input/output voltage -0.3v to +4.6v lvds output short circuit current (i osd ) continuous storage temperature range (t stg ) 65 q c to 150 q c maximum junction temperature (t j )150 q c lead temperature (t l ) (soldering, 4 seconds) 260 q c esd rating (hbm, 1.5 k : , 100 pf) i/o to gnd ! 10.0 kv all pins ! 6.5 kv esd rating (mm, 0 : , 200 pf) ! 400v supply voltage (v cc ) 3.0v to 3.6v operating temperature (t a )(note 7) 10 c to 70 c maximum supply noise voltage (v ccnpp ) 100 mv p-p (note 8) symbol parameter test conditions min typ max units transmitter lvttl input characteristics v ih input high voltage 2.0 v cc v v il input low voltage gnd 0.8 v v ik input clamp voltage i ik 18 ma 0.79 1.5 v i in input current v in 0.4v to 4.6v 1.8 10.0 p a v in gnd 10.0 0 transmitter lvds output characteristics (note 10) v od output differential voltage r l 100 : , see figure 1 250 tbd 450 mv ' v od v od magnitude change from differential low-to-high 35.0 mv v os offset voltage 1.125 1.25 1.375 v ' v os offset magnitude change from differential low-to-high mv i os short circuit output current v out 0v 3.5 5.0 ma i oz disabled output leakage current do 0v to 4.6v, pwrdn 0v r 1.0 r 10.0 p a transmitter supply current i ccwt 28:4 transmitter power supply current 32.5 mhz 31.0 49.5 ma for worst case pattern (with load) r l 100 : , 40.0 mhz 32.0 55.0 (note 11) see figure 3 66.0 mhz 37.0 60.5 85.0 mhz 42.0 66.0 i ccpdt powered down supply current pwrdn 0.8v 10.0 55.0 p a i ccgt 28:4 transmitter supply current 32.5 mhz 29.0 41.8 ma for 16 grayscale (note 11) see figure 21 40.0 mhz 30.0 44.0 (note 12) 65.0 mhz 35.0 49.5 85.0 mhz 39.0 55.0
7 www.fairchildsemi.com fin3385 fin3383 fin3384 fin3386 transmitter ac electrical characteristics over supply voltage and operating temperature ranges, unless otherwise specified. note 13: outputs of all transmitters stay in 3-state until power reaches 2v. both clock and data output begins to toggle 10ms after v cc reaches 3v and power-down pin is above 1.5v. note 14: this output data pulse position works for ttl inputs except the lvds output bit mapping difference (see figure 14). figure 16 s hows the skew between the first data bit and clock output. also 2-bit cycle delay is guaranteed when the msb is output from transmitter. note 15: this jitter specification is based on the assumption that pll has a ref clock with cycle-to-cycle input jitter less than 2ns. symbol parameter test conditions min typ max units t tcp transmit clock period see figure 5 11.76 t 50.0 ns t tch transmit clock (txclkin) high time 0.35 0.5 0.65 t t tcl transmit clock low time 0.35 0.5 0.65 t t clkt txclkin transition time (rising and failing) (10% to 90%) see figure 6 1.0 6.0 ns t jit txclkin cycle-to-cycle jitter 3.0 ns t xit txin transition time 1.5 6.0 ns lvds transmitter timing characteristics t tlh differential output rise time (20% to 80%) see figure 4 0.75 1.5 ns t thl differential output fall time (80% to 20%) 0.75 1.5 ns t stc txin setup to txclnin see figure 5 (f 85 mhz) 2.5 ns t htc txin holds to tclkin 0ns t tpdd transmitter power-down delay see figure 12, (note 13) 100 ns t tccd transmitter clock input to clock output delay (t a 25 q c and with v cc 3.3v) 5.5 ns transmitter clock input to clock output delay see figure 9 2.8 6.8 transmitter output data jitter (f 40 mhz) (note 14) t tppb0 transmitter output pulse position of bit 0 see figure 16 0.25 0 0.25 ns t tppb1 transmitter output pulse position of bit 1 a 0.25aa 0.25 ns t tppb2 transmitter output pulse position of bit 2 a 12a 0.25 2a 2a 0.25 ns t tppb3 transmitter output pulse position of bit 3 f x 7 3a 0.25 3a 3a 0.25 ns t tppb4 transmitter output pulse position of bit 4 4a 0.25 4a 4a 0.25 ns t tppb5 transmitter output pulse position of bit 5 5a 0.25 5a 5a 0.25 ns t tppb6 transmitter output pulse position of bit 6 6a 0.25 6a 6a 0.25 ns transmitter output data jitter (f 65 mhz) (note 14) t tppb0 transmitter output pulse position of bit 0 see figure 16 0.2 0 0.2 ns t tppb1 transmitter output pulse position of bit 1 a 0.2 a a 0.2 ns t tppb2 transmitter output pulse position of bit 2 a 12a 0.2 2a 2a 0.2 ns t tppb3 transmitter output pulse position of bit 3 f x 7 3a 0.2 3a 3a 0.2 ns t tppb4 transmitter output pulse position of bit 4 4a 0.2 4a 4a 0.2 ns t tppb5 transmitter output pulse position of bit 5 5a 0.2 5a 5a 0.2 ns t tppb6 transmitter output pulse position of bit 6 6a 0.2 6a 6a 0.2 ns transmitter output data jitter (f 85 mhz) (note 14) t tppb0 transmitter output pulse position of bit 0 see figure 16 0.2 0 0.2 ns t tppb1 transmitter output pulse position of bit 1 a 0.2 a a 0.2 ns t tppb2 transmitter output pulse position of bit 2 a 12a 0.2 2a 2a 0.2 ns t tppb3 transmitter output pulse position of bit 3 f x 7 3a 0.2 3a 3a 0.2 ns t tppb4 transmitter output pulse position of bit 4 4a 0.2 4a 4a 0.2 ns t tppb5 transmitter output pulse position of bit 5 5a 0.2 5a 5a 0.2 ns t tppb6 transmitter output pulse position of bit 6 6a 0.2 6a 6a 0.2 ns t jcc fin3385 transmitter clock out jitter f 40 mhz 350 370 ps (cycle-to-cycle) f 65 mhz 210 230 see figure 20 f 85 mhz 110 150 t tplls transmitter phase lock loop set time (note 15) see figure 22, (note 14) 10.0 ms
www.fairchildsemi.com 8 fin3385 fin3383 fin3384 fin3386 receiver dc electrical characteristics over supply voltage and operating temperature ranges, unless otherwise specified. (note 16) note 16: all typical values are at t a 25 q c and with v cc 3.3v. positive current values refer to the current flowing into device and negative values means current flowing out of pins. voltage are referenced to ground unless otherwise specified (except ' v od and v od ). note 17: the power supply current for the receiver can be different with the number of active i/o channels. note 18: total channel latency from sewrializer to deserializer is (t t tccd ). there is the clock period. note 19: receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bi t position. symbol parameter test conditions min typ max units lvttl/cmos dc characteristics v ih input high voltage 2.0 v cc v v il input low voltage gnd 0.8 v v oh output high voltage i oh 0.4 ma 2.7 3.3 v v ol output low voltage i ol 2ma 0.06 0.3 v v ik input clamp voltage i ik 18 ma 0.79 1.5 v i in input current v in 0v to 4.6v 10.0 10.0 p a i off input/output power off leakage current v cc 0v, r 10.0 p a all lvttl inputs/outputs 0v to 4.6v i os output short circuit current v out 0v 60.0 120 ma receiver lvds input characteristics v th differential input threshold high figure 2, table 2 100 mv v tl differential input threshold low figure 2, table 2 100 mv v icm input common mode range figure 2, table 2 0.05 2.35 v i in input current v in 2.4v, v cc 3.6v or 0v r 10.0 p a v in 0v, v cc 3.6v or 0v r 10.0 p a receiver supply current i ccwr 4:28 receiver power supply current 32.5 mhz 70.0 ma for worst case pattern (with load) c l 8 pf, 40.0 mhz 75.0 (note 17) see figure 3 66.0 mhz 114 85.0 mhz 135 i ccwr 3:21 receiver power supply current 32.5 mhz 49.0 60.0 ma for worst case pattern (with load) c l 8 pf, 40.0 mhz 53.0 65.0 (note 17) see figure 3 66.0 mhz 78.0 100 85.0 mhz 90.0 115 i ccpdt powered down supply current pwrdn 0.8v (rxout stays low) na 55.0 p a t rcop receiver clock output (rxclkout) period 11.76 t 50.0 t rcol rxclkout low time see figure 8 4.0 5.0 6.0 ns t rcoh rxclkout high time (f 85mhz) 4.5 5.0 6.5 ns t rsrc rxout valid prior to rxclkout (rising edge strobe) 3.5 ns t rhrc rxout valid after rxclkout 3.5 ns t rolh output rise time (20% to 80%) c l 8 pf, 2.0 3.5 ns t rohl output fall time (80% to 20%) see figure 4 1.8 3.5 ns t rccd receiver clock input to clock output delay see figure 20, (note 18) 3.5 5.0 7.5 ns t a 25 q c and v cc 3.3v t rpdd receiver power-down delay see figure 13 1.0 p s t rspb0 receiver input strobe position of bit 0 0.49 0.84 1.19 ns t rspb1 receiver input strobe position of bit 1 2.17 2.52 2.87 ns t rspb2 receiver input strobe position of bit 2 3.85 4.20 4.55 ns t rspb3 receiver input strobe position of bit 3 see figure 17 (f 85mhz) 5.53 5.88 6.23 ns t rspb4 receiver input strobe position of bit 4 7.21 7.56 7.91 ns t rspb5 receiver input strobe position of bit 5 8.89 9.24 9.59 ns t rspb6 receiver input strobe position of bit 6 10.57 10.92 11.27 ns t rskm rxin skew margin see figure 17, (note 19) 290 ps t rplls receiver phase lock loop set time see figure 11 10.0 ms
9 www.fairchildsemi.com fin3385 fin3383 fin3384 fin3386 receiver ac electrical characteristics (66mhz) note 20: for the receiver with falling-edge strobe, the definition of setup/hold time will be slightly different from the one with risin g-edge strobe. the clock ref- erence point is the time when the clock falling edge passes through 2v. for hold time t rhrc , the clock reference point is the time when falling edge passes through 0.8v. note 21: total channel latency from sewrializer to deserializer is (t t tccd ) (2*t t rccd ). there is the clock period. note 22: receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bi t position. symbol parameter test conditions min typ max units t rcop receiver clock output (rxclkout) period see figure 8 15.0 t 50.0 ns t rcol rxclkout low time 10.0 11.0 ns t rcoh rxclkout high time see figure 8 10.0 12.2 ns t rsrc rxout valid prior to rxclkout (rising edge strobe) 6.5 11.6 ns t rhrc rxout valid after rxclkout (f 40 mhz) 6.0 11.6 ns t rcol rxclkout low time 5.0 6.3 9.0 ns t rcoh rxclkout high time see figure 8, (note 20) 5.0 7.6 9.0 ns t rsrc rxout valid prior to rxclkout (rising edge strobe) 4.5 7.3 ns t rhrc rxout valid after rxclkout (f 66 mhz) 4.0 6.3 ns t rolh output rise time (20% to 80%) c l 8 pf, (note 20) 2.0 5.0 ns t rohl output fall time (80% to 20%) see figure 8 1.8 5.0 ns t rccd receiver clock input to clock output delay see figure 10, (note 21) 3.5 5.0 7.5 ns t a 25 q c and v cc 3.3v t rpdd receiver power-down delay see figure 13 1.0 p s t rspb0 receiver input strobe position of bit 0 1.0 1.4 2.15 ns t rspb1 receiver input strobe position of bit 1 4.5 5.0 5.8 ns t rspb2 receiver input strobe position of bit 2 see figure 17 8.1 8.5 9.15 ns t rspb3 receiver input strobe position of bit 3 (f 40 mhz) 11.6 11.9 12.6 ns t rspb4 receiver input strobe position of bit 4 15.1 15.6 16.3 ns t rspb5 receiver input strobe position of bit 5 18.8 19.2 19.9 ns t rspb6 receiver input strobe position of bit 6 22.5 22.9 23.6 ns t rspb0 receiver input strobe position of bit 0 0.7 1.1 1.4 ns t rspb1 receiver input strobe position of bit 1 2.9 3.3 3.6 ns t rspb2 receiver input strobe position of bit2 see figure 17 5.1 5.5 5.8 ns t rspb3 receiver input strobe position of bit 3 (f 65 mhz) 7.3 7.7 8.0 ns t rspb4 receiver input strobe position of bit 4 9.5 9.9 10.2 ns t rspb5 receiver input strobe position of bit 5 11.7 12.1 12.4 ns t rspb6 receiver input strobe position of bit 6 13.9 14.3 14.6 ns t rskm rxin skew margin f 40 mhz 490 ps see figure 17, (note 22) f 66 mhz 400 t rplls receiver phase lock loop set time see figure 11 10.0 ms
www.fairchildsemi.com 10 fin3385 fin3383 fin3384 fin3386 figure 1. differential lvds output dc test circuit note a: for all input pulses, t r or t f 1 ns. note b: c l includes all probe and jig capacitance. figure 2. differential receiver voltage definitions and propagation delay and transition time test circuit table 2. receiver minimum and maximum input threshold test voltages applied voltages resulting differential input voltage resulting common mode input voltage (v) (mv) (v) v ia v ib v id v ic 1.25 1.15 100 1.2 1.15 1.25 100 1.2 2.4 2.3 100 2.35 2.3 2.4 100 2.35 0.1 0 100 0.05 00.1 100 0.05 1.5 0.9 600 1.2 0.9 1.5 600 1.2 2.4 1.8 600 2.1 1.8 2.4 600 2.1 0.6 0 600 0.3 00.6 600 0.3
11 www.fairchildsemi.com fin3385 fin3383 fin3384 fin3386 ac loading and waveforms note: the worst case test pattern produces a maximum toggling of digital circuits, lvds i/o and lvttl/cmos i/o. depending on the vali d strobe edge of transmitter, the txclkin can be either rising or falling edge data strobe. figure 3. ? worst case ? test pattern figure 4. transmitter lvds output load and transition times figure 5. transmitter setup/hold and high/low times (rising edge strobe) figure 6. transmitter input clock transition time
www.fairchildsemi.com 12 fin3385 fin3383 fin3384 fin3386 ac loading and waveforms (continued) figure 7. transmitter outputs channel-to-channel skew note: for the receiver with falling-edge strobe, the definition of setup/hold time will be slightly different from the one with rising-edge strobe. the clock refer- ence point is the time when the clock falling edge passes through 2v. for hold time t rhrc , the clock reference point is the time when falling edge passes through 0.8v. figure 8. (receiver) setup/hold and high/low times figure 9. transmitter clock in to clock out delay (rising edge strobe) figure 10. receiver clock in to clock out delay (falling edge strobe)
13 www.fairchildsemi.com fin3385 fin3383 fin3384 fin3386 ac loading and waveforms (continued) figure 11. receiver phase lock loop set time figure 12. transmitter power-down delay figure 13. receiver power-down delay
www.fairchildsemi.com 14 fin3385 fin3383 fin3384 fin3386 ac loading and waveforms (continued) note: the information in this diagram shows the relationship between clock out and the first data bit. a 2-bit cycle delay is guarant eed when the msb is out- put from the transmitter. figure 14. 28 parallel lvttl inputs mapped to 4 serial lvds outputs note: this output data pulse position works for both transmitter with 28 or 21 ttl inputs except the lvds output bit mapping differe nce. all the information in this diagram tells that the skew between the first data bit and clock output. also 2-bit cycle delay is guaranteed when the msb is output from transmitter. figure 15. 21 parallel lvttl inputs mapped to 3 serial lvds outputs
15 www.fairchildsemi.com fin3385 fin3383 fin3384 fin3386 ac loading and waveforms (continued) figure 16. transmitter output pulse bit position figure 17. receiver input bit position
www.fairchildsemi.com 16 fin3385 fin3383 fin3384 fin3386 ac loading and waveforms (continued) note: t rskm is the budget for the cable skew and source clock skew plus isi (inter-symbol interference). note: the minimum and maximum pulse position values are based on the bit position of each of the 7 bits within the lvds data stream across pvt (process, voltage supply, and temperature). figure 18. receiver lvds input skew margin note: test setup used considers no requirement for separation of rms and deterministic jitter. other hardware setup such as wavecrest boxes can be used if no m1 software is available, but the test methodology in figure 20 should be followed. figure 19. transmitter clock out jitter measurement setup note: this jitter pattern is used to test the jitter response (clock out) of the device over the power supply range with worst jitter r 3ns (cycle-to-cycle) clock input. the specific test methodology is as follows: switching input data txin0 to txin20 at 0.5 mhz, and the input clock is shifted to left 3ns and to the right 3ns when data is high. the r 3 ns cycle-to-cycle input jitter is the static phase error between the two clock sources. jumping between two clock sources to simulate the worst case of clock edge jump (3 ns) from graphical controllers. cycle-to-cycle jitter at txclk out pin should be measured cross v cc range with 100mv noise (v cc noise frequency 2 mhz). figure 20. timing diagram of transmitter clock input with jitter
17 www.fairchildsemi.com fin3385 fin3383 fin3384 fin3386 ac loading and waveforms (continued) note: the 16-grayscale test pattern tests device power consumption for a ? typical ? lcd display pattern. the test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display. figure 21. ? 16 grayscale ? test pattern figure 22. transmitter phase lock loop time
www.fairchildsemi.com 18 fin3385 fin3383 fin3384 fin3386 low voltage 28-bit flat panel display link serializers/deserializers physical dimensions inches (millimeters) unless otherwise noted 56-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide package number mtd56 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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